Entropy in Spin Foam Models: The Statistical Calculation

Recently an idea for computing the entropy of black holes in the spin foam formalism has been introduced. Particularly complete calculations for the three dimensional euclidean BTZ black hole were done. The whole calculation is based on observables living at the horizon of the black hole universe. Departing from this idea of observables living at the horizon, we now go further and compute the entropy of BTZ black hole in the spirit of statistical mechanics. We compare both calculations and show that they are very interrelated and equally valid. This latter behaviour is certainly due to the importance of the observables.Comment: 11 pages, 1 figur

High brightness semiconductor lasers as transmitters for space lidar systems

High brightness semiconductor lasers are potential transmitters for future space lidar systems. In the framework of the European Project BRITESPACE, we propose an all-semiconductor laser source for an Integrated Path Differential Absorption lidar system for column-averaged measurements of atmospheric CO2 in future satellite missions. The complete system architecture has to be adapted to the particular emission properties of these devices using a Random Modulated Continuous Wave approach. We present the initial experimental results of the InGaAsP/InP monolithic Master Oscillator Power Amplifiers, providing the ON and OFF wavelengths close to the selected absorption line around 1572 nm

3D electronics for hybrid pixel detectors – TWEPP-09

Future hybrid pixel detectors are asking for smaller pixels in order to improve spatial resolution and to deal with an increasing counting rate. Facing these requirements is foreseen to be done by microelectronics technology shrinking. However, this straightforward approach presents some disadvantages in term of performances and cost. New 3D technologies offer an alternative way with the advantage of technology mixing. For the upgrade of ATLAS pixel detector, a 3D conception of the read-out chip appeared as an interesting solution. Splitting the pixel functionalities into two separate levels will reduce pixel size and open the opportunity to take benefit of technology's mixing. Based on a previous prototype of the read-out chip FE-I4 (IBM 130nm), this paper presents the design of a hybrid pixel read-out chip using threedimensional Tezzaron-Chartered technology. In order to disentangle effects due to Chartered 130nm technology from effects involved by 3D architecture, a first translation of FEI4 prototype had been designed at the beginning of this year in Chartered 2D technology, and first test results will be presented in the last part of this paper

HV/HR-CMOS sensors for the ATLAS upgrade—concepts and test chip results

In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given

Radiation-hard active pixel sensors for HL-LHC detector upgrades based on HV-CMOS technology

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

Low power discriminator for ATLAS pixel chip

The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers

Opportunities And Challenges of E-Health and Telemedicine Via Satelite

The introduction of Information and Communication Technology (ICT) in the health scenario is instrumental for the development of sustainable services of direct benefit for the European citizen. The setting up of satellite based applications will enhance rapidly the decentralisation and the enrichment of the European territory driving it towards a homogenous environment for healthcare

How to Handle Concomitant Asymptomatic Prosthetic Joints During an Episode of Hematogenous Periprosthetic Joint Infection:a Multicenter Analysis

BACKGROUND: Prosthetic joints are at risk of becoming infected during an episode of bacteremia, especially during Staphylocococcus aureus bacteremia. However, it is unclear how often asymptomatic periprosthetic joint infection (PJI) occurs, and whether additional diagnostics should be considered. METHODS: In this multicenter study, we retrospectively analyzed a cohort of patients with a late acute (hematogenous) PJI between 2005-2015 who had concomitant prosthetic joints in situ. Patients without at least 1 year of follow-up were excluded. RESULTS: We included 91 patients with a hematogenous PJI and 108 concomitant prosthetic joints. The incident PJI was most frequently caused by Staphylococcus aureus (43%), followed by streptococci (26%) and Gram-negative rods (18%). Of 108 concomitant prosthetic joints, 13 were symptomatic, of which 10 were subsequently diagnosed as a second PJI. Of the 95 asymptomatic prosthetic joints, 1 PJI developed during the follow-up period and was classified as a "missed" PJI at the time of bacteremia with S. aureus (1.1%). Infected prosthetic joints were younger than the noninfected ones in 67% of cases, and prosthetic knees were affected more often than prosthetic hips (78%). CONCLUSIONS: During an episode of hematogenous PJI, concomitant asymptomatic prosthetic joints have a very low risk of being infected, and additional diagnostic work-up for these joints is not necessary

EU-wide methodology to map and assess ecosystem condition

The EU Biodiversity Strategy for 2030 calls for developing an EU-wide methodology to map, assess and achieve good condition of ecosystems, so they can deliver benefits to society through the provision of ecosystem services. The EU-wide methodology presented in this report addresses this methodological gap. The EU-wide methodology has adopted the System of Environmental Economic Accounting - Ecosystem Accounting (SEEA EA) as reference framework. The SEEA EA is an integrated framework for organizing biophysical information about ecosystems, adopted as a global statistical standard by the United Nations. The SEEA EA is also the reference framework under the proposal for the amendment of Regulation (EU) No 691/2011 on European environmental economic accounts. Building on previous work done within the MAES initiative, the EU-wide methodology presents useful insights to operationalise the SEEA EA at EU level by integrating different EU data streams in a consistent way with this global statistical standard to consistently map and assess ecosystem condition in the EU across all ecosystem types. The adoption of the SEEA EA framework offers the flexibility to integrate different data flows, leveraging the use of available EU data, such as data reported by MS under EU legislation and EU geospatial data. The EU-wide methodology. The implementation of the EU-wide methodology, making use of available data, will provide the scientific knowledge base to support a range of policies and legal instruments